1. Field of the Invention
This invention relates to a semiconductor device and, in particular, to a semiconductor device having resistance variable memory cells.
2. Description of the Related Art
A resistance variable memory cell includes a memory element for storing information as variation in resistance. A voltage at a predetermined level is applied to a memory element serially connected to a load with a predetermined resistance, whereby an output voltage corresponding to the resistance of the memory element can be obtained at a node between the memory element and the load. Information written in the memory element is read out by comparing this output voltage with a reference voltage.
The reference voltage is obtained by applying a voltage at a predetermined level to a reference resistance element serially connected to a load having a predetermined resistance.
In the case of a semiconductor device having a single reference resistance element for a plurality of memory cells, it may be impossible to read information from more than an allowable number of memory cells depending on characteristics of the memory cells. Techniques therefore have been proposed to make the resistance value of the reference resistance variable so that the resistance of the reference resistance element is set according to characteristics of a plurality of memory cells. This type of technique is described for example in Japanese Laid-Open Patent Publication No. 2005-18916 (Patent Document 1) and Japanese Laid-Open Patent Publication No. 2005-50424 (Patent Document 2).
Patent Document 1 describes a technique in which characteristics of memory cells and a reference cell are tested, and information is written in the reference cell based on the test result to set the resistance value of the reference resistance. However, I have now discovered that Patent Document 1 does not describe at all how to set a reference potential when there are a large number of memory cells and there is resistance distribution. Consequently, the semiconductor device described in Patent Document 1 has a drawback that it is impossible to set the resistance value of the reference resistance more appropriately when there is resistance distribution among a plurality of memory cells.
As for a semiconductor device described in Patent Document 2, a lower limit of resistance distribution in the high-resistance state of all the memory cells and a higher limit of the resistance distribution in the low-resistance state are obtained, and a mean value of these lower and higher limits is set as a resistance value of the reference resistance. Consequently, this semiconductor device also has a drawback, similarly to the one described in Patent Document 1, that it is impossible to set the resistance value of the reference resistance more appropriately according to the resistance distribution.